Dr. Debiprasanna Sahoo

Publications

1Formal Modeling and Verification of Security Properties of a Ransomware-Resistant SSD, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), Vol-42(8), 2022
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, and Madhu Mutyam
2Formal Modeling and Verification of a Victim DRAM Cache, ACM Transactions on Design Automation of Electronic Systems (TODAES), Vol-24(2), 2019
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha
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3ReDRAM: A Reconfigurable DRAM Cache for GPGPUs, IEEE Computer Architecture Letter (CAL), vol-17, issue-2, 2018
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam
4Formal Modeling and Verification of Controllers for a Family of DRAM Caches, IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems (TCAD), vol-37, issue-11, 2018
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, S. Ramesh, Partha
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1Predicting Memory Access Latency using Machine Learning,
AMD Global Technology Conference, 2021
Shivam Potdar, Vanchinathan Venkataramani, Scot Weber, Monica Farkash, Debiprasanna Sahoo, GS Nitesh Narayana, Surya Teja Parisa
2Slumber: Static Power Management for GPGPU Register Files, 25th, International Symposium on Low Power Electronics and Design, ACM, 2020
Devashree Tripathy, H.Z. Sabzi, Debiprasanna Sahoo, Manoranjan Satpathy, Laxmi
Narayan Bhuyan
3Fuzzy Fairness Controller for NVMe SSDs, 34th, International Conference on Supercomputing (ICS), IEEE, 2020
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
4Post-Model Validation of Victim DRAM Caches, 37th, International Conference on Computer Design (ICCD), IEEE, 2019
Debiprasanna Sahoo, Shivani Tripathy, Manoranjan Satpathy, Madhu Mutyam
5Formal Modeling and Verification of of NAND Flash Memory, 37th, International Conference on Computer Design (ICCD), IEEE, 2019
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy, Srinivas Pinisetty
6Multidimensional Grid Aware Address Prediction for GPGPU, 32nd, International Conference on VLSI Design (VLSID), IEEE, 2019
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy
7CAMO: A Novel Cache Management Organization for GPGPUs, 23rd, Asia and South Pacific Design Automation Conference (ASP-DAC), ACM, 2018
Debiprasanna Sahoo, Swaraj Sha, Manoranjan Satpathy, Madhu Mutyam, Laxmi
Narayan Bhuyan
8Locking Lines in Tag Cache to Improve Access Optimization for DRAM Caches, International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), ESWEEK, IEEE, 2018
Shivani Tripathy, Debiprasanna Sahoo, Manoranjan Satpathy
9An Experimental Study on Dynamic Bank Partitioning of DRAM in Chip Multiprocessors, 30th, International Conference on VLSI Design (VLSID), IEEE, 2017
Debiprasanna Sahoo, Manoranjan Satpathy, Madhu Mutyam
10MSimDRAM: Formal Model Driven Development of DRAM Simulator, 29th, International Conference on VLSI Design (VLSID), IEEE, 2016
Debiprasanna Sahoo, Manoranjan Satpathy