Dr. Nijwm Wary

Publications

1Suraj Kumar P., V. K. Surya and N. Wary, “Energy Efficient Integrated Summer and Latch Based DFE With Reduced Tap Loading”, IEEE Transactions on Circuits and Systems II, 2023. (accepted for publication)
2S. K. Prusty, S. P. Dash, V. K. Surya, and N. Wary, “Differential evolution based adaptation algorithm for multi-stage continuous time linear equalizer,” IEEE Transactions on Components, Packaging and Manufacturing Technology, vol. 13, no. 12, pp. 2046-2049, Dec. 2023.
3P. Chandrika Kondeti, Suraj Kumar P. and N. Wary, ”Current-Integrating Summer for DFE Receiver With Low Common Mode Variation”, Microelectronics Journal, Elsevier, Vol. 123, May 2022
4X. Mo, J. Wu, N. Wary and T. C. Carusone, “Design Methodologies for Low-Jitter CMOS Clock Distribution,” in IEEE Open Journal of the Solid-State Circuits Society, vol. 1, pp. 94-103, 2021.
5B. Vatankhahghadim, N. Wary, J. Bailey and A.Chan Carusone, ”A Study of Discrete Multitone Modulation for Wireline Links Beyond 100 Gb/s”, IEEE Open Journal of Circuits and Systems, vol. 2, pp. 78-90, 2021
6A. R. Chowdhury, N. Wary and P. Mandal, “Hybrid Bidirectional Transceiver for Multipoint-to-Multipoint Signaling Across On-Chip Global Interconnects”, IET Circuit, Devices and System, Vol. 14, Issue 6, pp. 780-787, Sept. 2020
7B. Dehlaghi, N. Wary and A.Chan Carusone, “Ultra-Short-Reach Interconnects for Die-to-Die Links”, IEEE Solid-State Circuits Magazine, vol. 11, no. 2, pp. 42-53, Spring 2019.
8 N. Wary and P. Mandal, “Current-Mode Full-Duplex Transceiver for Lossy On-Chip Global Interconnects”, IEEE Journal of Solid-State Circuits, vol. 52, no. 8, pp. 2026-2037, Aug. 2017.
9N. Wary and P. Mandal, “Current-Mode Triline Transceiver for Coded Differential Signaling Across On-Chip Global Interconnects”, IEEE Transactions on Very Large Scale Integration, vol. 25, no. 9, pp. 2575-2587, Sept. 2017.
10N. Wary and P. Mandal, “High Speed Energy Efficient Bi-directional Transceiver for On-Chip Global Interconnects”, IET Circuit, Devices and System, Vol.9, Issue 5, pp. 319-327, Sept. 2015.
11N. Wary and P. Mandal, “A low impedance receiver for power efficient current mode signalling across on-chip global interconnects”, International Journal Electronic and Communication, Elsevier, Vol. 68, No. 10, pp. 969-975, Oct 2014.
1Sahil Dalvi, Pilli Kalyan Kumar, Olive Ray and N. Wary, “A Fully Integrated SCC DC-DC Converter with Novel FMC Controller for Fast Transient Response”, 21st IEEE Interregional NEWCAS Conference, Edinburgh, Scotland, June 2023.
2Suraj Kumar P., V. K. Surya and N. Wary, “A High-Speed Charge-Injection based Double Tail Latch for Decision Feedback Equalizer (DFE)”, 21st IEEE Interregional NEWCAS Conference, Edinburgh, Scotland, June 2023.
3V. K. Surya, Suraj Kumar P. and N. Wary, “A 26 Gb/s Echo-Cancellation Based Simultaneous Bidirectional Transceiver in 65 nm CMOS”, IEEE International Symposium on Circuits & Systems, Monterey, California, 2023.
4Nishant Maurya and N. Wary, ”Design and Analysis of PVT Invariant Current Reference in 65-nm CMOS”, 65th IEEE International Midwest Symposium on Circuits and Systems, Fukuoka, Japan, 2022.
5Prema Kumar G., N. Wary and Vijaya Sankara Rao P., “Power Efficient Echo-Cancellation Based Hybrid forFull-Duplex Chip-to-Chip Interconnects”, IEEE International Symposium on Circuits & Systems, Texas, Austin, 2022.
6Prema Kumar G., N. Wary and Vijaya Sankara Rao P., “Low-Power Half-Rate Charge-Steering Hybrid for Full-Duplex Chip-to-Chip Interconnects”, IEEE International Symposium on Circuits & Systems, Texas, Austin, 2022. (accepted)
7B. Vatankhahghadim, N. Wary and A.Chan Carusone, “Discrete Multitone Signalling for wireline Communication”, IEEE International Symposium on Circuits & Systems, Seville, Spain, Oct. 12-14, 2020.
8P. Chen, N. Wary and A.Chan Carusone,”All-Digital Calibration Algorithms to Correct for Static Non-Linearities in ADCs”, IEEE International Symposium on Circuits & Systems, Seville, Spain, Oct 12-14, 2020.
9A. R. Chowdhury, N. Wary and P. Mandal, “A Regulated-Cascode Based Current-Integrating TIA RX with 1-Tap Speculative Adaptive DFE”, 2019 62nd IEEE International Midwest Symposium on Circuits and Systems, Dallas, TX, USA, 2019, pp. 790-793.
10A. R. Chowdhury, N. Wary and P. Mandal, “Energy Efficient Bidirectional Equalized Transceiver with PVT Insensitive Active Termination”, 2019 32th International Conference on VLSI Design and 2019 18th International Conference on Embedded Systems (VLSID), Delhi, Jan 2019, pp.25-30.
11N. Wary and P. Mandal,”Current-Mode Simultaneous Bidirectional Transceiver for On-Chip Global Interconnects”, Quality Electronic Design (ASQED), 2015 6th Asia Symposium on,Kuala Lumpur, Aug. 2015, pp. 19-24.
X. Mo, N. Wary, and A. Chan Carusone, “High-Performance CMOS Clock Distribution,”  in Phase-Locked Frequency Generation and Clocking: Architectures and circuits for modern wireless and wireline systems, Editor W. Rhee, The Institution of Engineering and Technology, 2020. [Link]